LAN9312 datasheet(43/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

Revision 1.2 (04-08-08)

DATASHEET

manual_FC_strap_1

Port 1 Manual Flow Control Enable Strap: Configures the

default value of the Port 1 Full-Duplex Manual Flow Control

Select (MANUAL_FC_1) bit in the Port 1 Manual Flow

Control Register (MANUAL_FC_1). When configured low,

flow control is determined by auto-negotiation (if enabled),

and symmetric PAUSE is advertised (bit 10 of the Port x

PHY Auto-Negotiation Advertisement Register

(PHY_AN_ADV_x) is set).

When configured high, flow control is determined by the

Port 1 Full-Duplex Transmit Flow Control Enable

(TX_FC_1) and Port 1 Full-Duplex Receive Flow Control

Enable (RX_FC_1) bits, and symmetric PAUSE is not

advertised (bit 10 of the Port x PHY Auto-Negotiation

Advertisement Register (PHY_AN_ADV_x) is cleared).

auto_mdix_strap_2

Port 2 Auto-MDIX Enable Strap: Configures the default

value for the Auto-MDIX functionality on Port 2 when the

AMDIXCTL bit in the Port x PHY Special Control/Status

Indication Register

(PHY_SPECIAL_CONTROL_STAT_IND_x) is cleared.

When configured low, Auto-MDIX is disabled. When

configured high, Auto-MDIX is enabled.

Note:

If AMDIXCTL is set, this strap had no effect.

AUTO_MDIX_2

manual_mdix_strap_2

Port 2 Manual MDIX Strap: Configures MDI(0) or MDIX(1)

for Port 2 when the auto_mdix_strap_2 is low and the

AMDIXCTL bit of the Port x PHY Special Control/Status

Indication Register

(PHY_SPECIAL_CONTROL_STAT_IND_x) is cleared.

autoneg_strap_2

Port 2 Auto Negotiation Enable Strap: Configures the

default value for the Auto-Negotiation (PHY_AN) enable bit

in the PHY_BASIC_CTRL_2 register (See

Section 14.4.2.1). When configured low, auto-negotiation is

disabled. When configured high, auto-negotiation is

enabled.

This strap also affects the default value of the following bits:

PHY_SPEED_SEL_LSB and PHY_DUPLEX bits of the

Port x PHY Basic Control Register

(PHY_BASIC_CONTROL_x)

10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex

(bit 5) bits of the Port x PHY Auto-Negotiation

Advertisement Register (PHY_AN_ADV_x)

MODE[2:0] bits of the Port x PHY Special Modes Register

(PHY_SPECIAL_MODES_x)

Refer to the respective register definition sections for

additional information.

Table 4.2 Soft-Strap Configuration Strap Definitions (continued)

STRAP NAME

DESCRIPTION

PIN / DEFAULT

VALUE

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