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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

Revision 1.2 (04-08-08)

DATASHEET

The following sections detail each category of interrupts and their related registers. Refer to

Chapter 14, "Register Descriptions," on page 166 for bit-level definitions of all interrupt registers.

5.2.1

1588 Time Stamp Interrupts

Multiple 1588 Time Stamp interrupt sources are provided by the LAN9312. The top-level 1588_EVNT

(bit 29) of the Interrupt Status Register (INT_STS) provides indication that a 1588 interrupt event

occurred in the 1588 Interrupt Status and Enable Register (1588_INT_STS_EN).

The 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) provides enabling/disabling and

status of all 1588 interrupt conditions. These include TX/RX 1588 clock capture indication on Ports

2,1,0, 1588 clock capture for GPIO[8:9] events, as well as 1588 timer interrupt indication.

In order for a 1588 interrupt event to trigger the external IRQ interrupt pin, the desired 1588 interrupt

event must be enabled in the 1588 Interrupt Status and Enable Register (1588_INT_STS_EN), bit 29

(1588_EVNT_EN) of the Interrupt Enable Register (INT_EN) must be set, and IRQ output must be

enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG).

For additional details on the 1588 Time Stamp interrupts, refer to Section 11.6, "IEEE 1588 Interrupts,"

on page 160.

5.2.2

Switch Fabric Interrupts

Multiple Switch Fabric interrupt sources are provided by the LAN9312 in a three-tiered register

structure as shown in Figure 5.1. The top-level SWITCH_INT (bit 28) of the Interrupt Status Register

(INT_STS) provides indication that a Switch Fabric interrupt event occurred in the Switch Engine

Interrupt Pending Register (SWE_IPR).

In turn, the Switch Engine Interrupt Pending Register (SWE_IPR) and Switch Engine Interrupt Mask

(Buffer Manager, Switch Engine, and Port 2,1,0 MACs).

The low-level Switch Fabric sub-module interrupt pending and mask registers of the Buffer Manager,

Switch Engine, and Port 2,1,0 MACs provide multiple interrupt sources from their respective sub-

modules. These low-level registers provide the following interrupt sources:

Buffer Manager (Buffer Manager Interrupt Mask Register (BM_IMR) and Buffer Manager Interrupt

Pending Register (BM_IPR))

—Status B Pending

—Status A Pending

Switch Engine (Switch Engine Interrupt Mask Register (SWE_IMR) and Switch Engine Interrupt

Pending Register (SWE_IPR))

—Interrupt Pending

Port 2,1,0 MACs (Port x MAC Interrupt Mask Register (MAC_IMR_x) and Port x MAC Interrupt

Pending Register (MAC_IPR_x))

—No currently supported interrupt sources. These registers are reserved for future use.

In order for a Switch Fabric interrupt event to trigger the external IRQ interrupt pin, the following must

be configured:

The desired Switch Fabric sub-module interrupt event must be enabled in the corresponding mask

Interrupt Mask Register (SWE_IMR) for the Switch Engine, and/or Port x MAC Interrupt Mask

The desired Switch Fabric sub-module interrupt event must be enabled in the Switch Engine

Interrupt Mask Register (SWE_IMR)

Bit 28 (SWITCH_INT_EN) of the Interrupt Enable Register (INT_EN) must be set

IRQ output must be enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG)

For additional details on the Switch Fabric interrupts, refer to Section 6.6, "Switch Fabric Interrupts,"

on page 81.

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