LAN9312 datasheet(48/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

SMSC LAN9312

DATASHEET

The Port 1 & 2 PHY energy-detect events are capable of asserting the PME output by additionally

setting the PME_EN and ED_EN2 (Port 2 PHY) or ED_EN1 (Port 1 PHY) bits of the Power

Management Control Register (PMT_CTRL).

4.3.2

Host MAC Power Management

The Host MAC provides wake-up frame and magic packet detection modes. When enabled in the Host

MAC Wake-up Control and Status Register (HMAC_WUCSR) (via the WUEN bit for wake-up frames,

and the MPEN bit for magic packets), detection of wake-up frames or magic packets causes the WUFR

and MPR bits of the HMAC_WUCSR register to set, respectively. If either of the WUFR and MPR bits

are set, the WOL_STS bit of the Power Management Control Register (PMT_CTRL) will be set. These

events can enable PME output assertion by additionally setting the PME_EN bit of the Power

Management Control Register (PMT_CTRL).

The IRQ interrupt output can be triggered by a wake-up frame or magic packet as described in Section

5.2.6, "Power Management Interrupts," on page 53.

Refer to Section 9.5, "Wake-up Frame Detection," on page 116 and Section 9.5.1, "Magic Packet

Detection," on page 118 for additional details on these features.

LAN9312 Scheda tecnica(PDF) 48 Page - SMSC Corporation