DIO7S104

Version 1.5, Dec 2025

www.dioo.com

© 2025 Dioo Microcircuits Co., Ltd. Jiangsu

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10.Function Description

10.1. Power up and power down sequence

The DIO7S104 has an output enable pin which control the output status. When the OE input is low, all I/Os are

placed in the high-impedance state. To ensure the high-impedance state during power up or power down, OE

should be connected to GND via a pull-down resistor. Pins of A port and OE are referenced to VCCA and pins of B

port are referenced to VCCB.

Figure 7. Power up and power down sequence, tup / tdown ≥ 100 μs

10.2. Architecture

The DIO7S104 architecture (See Figure 8) does not require a direction-control signal to regulate the direction of

data flow from A to B or from B to A. The output drivers of the device maintain high or low, but are designed to be

weak, in a DC state. As a result, when data on the bus flows to the opposite direction, an external driver can

overdrive the output drivers.

The output one-shots on the A or B ports detect rising or falling edges. During a rising edge, the one-shot turns

on the PMOS transistors (T1, T2) for a short duration, which speeds up the low-to-high transition. During a falling

edge, the one-shot turns on the NMOS transistors (T3, T4) for a short duration, which speeds up the high-to-low

transition. 70 Ω at VCCO = 1.2 V to 1.8 V, 50 Ω at VCCO = 1.8 V to 3.3 V, and 40 Ω at VCCO = 3.3 V to 5 V is the

normal output impedance during output transition.

Figure 8. Architecture of DIO7S104 device I/O cell