RA4L1 datasheet(107/125 Pages) RENESAS

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Table 2.77

Code flash characteristics (3) (2 of 2)

Middle-speed operating mode

Conditions: VCC = AVCC0 = 1.6 to 3.6 V

Parameter

Symbol

ICLK = 1 MHz

ICLK = 8 MHz*1

Unit

Min

Typ

Max

Min

Typ

Max

Erase suspended time

tSED

—

33.4

—

13.1

µs

Forced stop time

tFD

—

33.4

—

13.1

µs

Configuration Set time

tCFGS

—

494

—

277

Flash memory mode transition wait

time 1

tDIS

—

µs

Flash memory mode transition wait

time 2

tMS

—

µs

Note:

Does not include the time until each operation of the flash memory is started after instructions are executed by software.

Note:

The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory.

Note:

The frequency accuracy of FCLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy

of the clock source.

Note 1. When 1.8 V ≤ VCC = AVCC0 ≤ 3.6 V

Table 2.78

Code flash characteristics (4)

Low-speed operating mode

Conditions: VCC = AVCC0 = 1.6 to 3.6 V

Parameter

Symbol

ICLK = 1 MHz

Unit

Min

Typ

Max

Programming time

8-byte

tP8

—

128

1064

µs

Erasure time

2-KB

tE2K

—

14.1

390

Blank check time

8-byte

tBC8

—

67.7

µs

2-KB

tBC2K

—

7538

µs

Erase suspended time

tSED

—

33.4

µs

Forced stop time

tFD

—

33.4

µs

Configuration Set time

tCFGS

—

494

Flash memory mode transition wait time 1

tDIS

—

µs

Flash memory mode transition wait time 2

tMS

—

µs

Note:

Does not include the time until each operation of the flash memory is started after instructions are executed by software.

Note:

The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory.

Note:

The frequency accuracy of FCLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy

of the clock source.

2.13.2

Data Flash Memory Characteristics

Table 2.79

Data flash characteristics (1)

Parameter

Symbol

Min

Typ

Max

Unit

Conditions

Reprogramming/erasure cycle*1

NDPEC

100000

1000000

—

Times

—

Data hold time

After 10000 times of NDPEC

tDDRP

20*2 *3

—

Year

Ta = +105 °C

10*2 *3

—

Ta = +125 °C

After 100000 times of NDPEC

5*2 *3

—

Ta = +105 °C

After 1000000 times of NDPEC

—

1*2 *3

—

Ta = +25 °C

Note 1. The reprogram/erase cycle is the number of erasure for each block. When the reprogram/erase cycle is n times (n = 100,000),

erasing can be performed n times for each block. For instance, when 1-byte programming is performed 256 times for different

addresses in 256-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,

programming the same address for several times as one erasure is not enabled. (overwriting is prohibited.)

Note 2. Characteristics when using the flash memory programmer and the self-programming library provided by Renesas Electronics.

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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