RA4L1 datasheet(109/125 Pages) RENESAS

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Note:

The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory.

Note:

The frequency accuracy of FCLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy

of the clock source.

2.13.3

Serial Wire Debug (SWD)

Table 2.83

SWD characteristics (1)

Conditions: VCC = AVCC0 = 2.4 to 5.5 V

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

SWCLK clock cycle time

tSWCKcyc

—

Figure 2.72

SWCLK clock high pulse width

tSWCKH

—

SWCLK clock low pulse width

tSWCKL

—

SWCLK clock rise time

tSWCKr

—

SWCLK clock fall time

tSWCKf

—

SWDIO setup time

tSWDS

—

Figure 2.73

SWDIO hold time

tSWDH

—

SWDIO data delay time

tSWDD

—

Table 2.84

SWD characteristics (2)

Conditions: VCC = AVCC0 = 1.6 to 2.4 V

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

SWCLK clock cycle time

tSWCKcyc

250

—

Figure 2.72

SWCLK clock high pulse width

tSWCKH

120

—

SWCLK clock low pulse width

tSWCKL

120

—

SWCLK clock rise time

tSWCKr

—

SWCLK clock fall time

tSWCKf

—

SWDIO setup time

tSWDS

—

Figure 2.73

SWDIO hold time

tSWDH

—

SWDIO data delay time

tSWDD

—

170

tSWCKH

tSWCKf

tSWCKcyc

SWCLK

tSWCKr

tSWCKL

Figure 2.72

SWD SWCLK timing

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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