STA680 datasheet(24/43 Pages) STMICROELECTRONICS

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Operation and general remarks

STA680

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4.2.2

Oscillator setting time

Once the power supply has reached the operating level, the internal voltage regulator gets

functional after TDC1V8 = 300 µs (see Table 4) and starts supplying the 1.8 V voltage to

internal IPs such as PLLs and Crystal Oscillator.

The PLL is powered up but not yet functioning since the internal logic keeps it in bypass

mode until a stable clock is available and STA680 has entered the secondary boot phase.

As shown in Figure 8, if an external crystal is connected to the internal oscillator this will

output a correct waveform after TOSC = 0.18 ms (seeTable 4).

At this time, if no crystal is used, a digital clock must be supplied according to the

instructions detailed in Section 4.1.

Either if an external crystal is used or the reference clock is provided through a digital

source, the RESET_N pin must be kept low for an additional TRST = 1.1 µs.

As described in Section 4.1 the internal clock configuration is defined latching on the rising

edge of the RESET_N signal the value of the pins ADAT3, BLEND and DAC256X; the value

of this three signals must be stable at least TCFG = 0.1 µs before the leading edge of the

RESET_N signal.

4.2.3

Boot sequence

Once the RESET_N signal has been released and the power up sequence correctly

performed, the STA680 enters the boot procedure, which consists of two phases consisting

of device setup and application authentication and download.

During the first phase the STA680 executes the on-chip primary boot code contained in the

32 kilobyte Boot ROM. The primary boot synchronizes the internal cores, initializes the SPI

and IIC interfaces and automatically selects the secondary boot code source by searching a

pre-defined pattern into UART1, Flash, SPI1, IIC1 and IIC2.

Once the device on which the secondary boot resides has been found, following tasks are

performed: the code is authenticated, the SDRAM is initialized and the secondary boot code

is downloaded into it.

The downloading speed depends on the device reference clock frequency even if this

parameter does not have a big impact on the overall boot time since the dimension of this

part of the code is small.

During the second phase of the boot procedure to achieve acceptable boot time the STA680

performs PLLs setup and takes the internal clock frequency to 28.224 MHz (see Figure 8)

then downloads and validates the application code from the external Flash memory. This

last task ends the boot procedure.

4.2.4

Normal operation mode

After the execution of the boot code, the device enters the normal operation mode by

jumping to the main program loop.

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