STA680 datasheet(33/43 Pages) STMICROELECTRONICS

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STA680

Digital I/O and memory interfaces

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The data pins of the two I2C interfaces are open drain drivers and must have resistive pull-

up conforming to Philip's IIC specification.

Figure 12 shows timing diagrams and waveform for the two I2C interfaces.

Figure 12.

Timing diagrams and waveform for the two I2C interfaces

In Table 15 are reported the timing values for the I2C interface.

Table 14.

Host and auxiliary I2C interface pin list

Pin name

Designation

Type

Drive

IIC1_SCL

Host Micro I2C interface serial clock line

I/O

4mA

IIC1_SDA

Host Micro I2C interface serial data line

I/O

4mA

IIC1_DA

Host Micro I2C interface data acknowledged

I/O

4mA

IIC2_SCL

Auxiliary I2C interface serial clock line

I/O

4mA

IIC2_SDA

Auxiliary I2C interface serial data line

I/O

4mA

IIC2_DA

Auxiliary I2C interface data acknowledged

I/O

4mA

Ts,dat

Th,dat

Thigh

IICx_SDA

IICx_SCL

Bit 1

Bit 2

Bit n

Start

Stop

1/Fscl

Tlow

Th,sta

Th,sto

AC00719

Table 15.

I2C interface timing values

Symbol

Parameter

Condition

Standard-mode

Fast-mode

Unit

Min.

Max.

Min.

Max.

Fscl

Scl clock frequency

100

400

kHz

Tlow

Low period of scl clock

4.7

1.3

µs

Thigh

High period of scl clock

0.6

µs

Th,dat

Data hold time

µs

Ts,dat

Data setup time

250

100

µs

Th,sta

Hold time for start condition

0.6

µs

Ts,sto

Setup time for stop

condition

40.6

µs

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