R8C datasheet(157/199 Pages) RENESAS

157 / 199 page

R8C/10 Group

Rev.1.20 Jan 27, 2006

page 147 of 180

REJ09B0019-0120

Figure 17.4 FMR1 and FMR4

Flash memory control register 4

SymbolAddressAfter reset

FMR401B316

010000002

b7 b6 b5 b4 b3 b2 b1 b0

Bit symbol

Bit name

Function

Erase-suspend request bit(2)

0: Erase restart

1: Erase-suspend request

FMR41

Erase-suspend function

enable bit(1)

0: Invalid

1: Valid

Read status flag

0: Disable reading

1: Enable reading

FMR40

FMR46

Reserved bit

Set to “0”

(b7)

Reserved bit

Set to “0”

(b5-b2)

NOTES:

1. To set this bit to “1”, write “0” and then “1” in succession. Make sure no interrupts will occur before

writing “1” after writing “0”.

2. This bit is valid only when the FMR40 bit is set to “1” (valid) and can only be written before ending an

erase after issuing an erase command. Other than this period, this bit is set to “0”.

In EW0 mode, this bit can be set to “0” and “1” by program.

In EW1 mode, this bit is automatically set to “1” if a maskable interrupt occurs during an erase operation

while the FMR40 bit is set to “1”. This bit can not be set to “1” by program. (Can be set to “0”.)

Flash memory control register 1

SymbolAddressAfter reset

FMR101B516

0100XX0X2

b7 b6 b5 b4 b3 b2 b1 b0

Bit symbol

Bit nameFunction

EW1 mode select bit(1)

0: EW0 mode

1: EW1 mode

FMR11

Reserved bit

Set to “0”

Reserved bit

When read, its content is

indeterminate.

Reserved bit

Set to “0”

(b0)

(b5-b4)

(b7)

Reserved bit

When read, its content is

indeterminate.

(b3-b2)

NOTES:

1. To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no

interrupts will occur before writing “1” after writing “0”.

The FMR01 and FMR11 bits both are set to “0” by setting the FMR01 bit to “0”.

Nothing is assigned.

When write, set to “0”.

(b6)

17.4 CPU Rewrite Mode

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