H8SX1663 datasheet(363/1158 Pages) RENESAS

363 / 1158 page

Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 311 of 1102

REJ09B0294-0100

6.16

Bus Arbitration

This LSI has bus arbiters that arbitrate bus mastership operations (bus arbitration). This LSI

incorporates internal access and external access bus arbiters that can be used and controlled

independently. The internal bus arbiter handles the CPU, DTC, and DMAC accesses. The external

bus arbiter handles the external access by the CPU, DTC, and DMAC, refresh, and external bus

release request (external bus master).

The bus arbiters determine priorities at the prescribed timing, and permit use of the bus by means

of the bus request acknowledge signal.

6.16.1

Operation

The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus

request acknowledge signal to the bus master. If there are bus requests from more than one bus

master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus

master receives the bus request acknowledge signal, it takes possession of the bus until that signal

is canceled.

The priority of the internal bus arbitration:

DMAC > DTC > CPU

The priority of the external bus arbitration:

Refresh > External bus release request > External access by the CPU, DTC, or DMAC

If the DMAC or DTC accesses continue, the CPU can be given priority over the DMAC or DTC

to execute the bus cycles alternatively between them by setting the IBCCS bit in BCR2. In this

case, the priority between the DMAC and DTC does not change.

An internal bus access by the CPU, DTC, or DMAC, an external bus release, and the refresh can

be executed in parallel.

H8SX1663 Scheda tecnica(PDF) 363 Page - Renesas Technology Corp