HD6432142 datasheet(233/1177 Pages) RENESAS

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Section 7 Data Transfer Controller (DTC)

Rev. 4.00 Sep 27, 2006 page 189 of 1130

REJ09B0327-0400

7.2.9

Module Stop Control Register (MSTPCR)

MSTP15

R/W

Bit

Initial value

Read/Write

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRH

MSTPCRL

MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.

When the MSTP14 bit in MSTPCR is set to 1, the DTC operation stops at the end of the bus cycle

and a transition is made to module stop mode. Note that 1 cannot be written to the MSTP14 bit

when the DTC is being activated. For details, see section 25.5, Module Stop Mode.

MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

MSTPCRH Bit 6—Module Stop (MSTP14): Specifies the DTC module stop mode.

MSTPCRH

Bit 6

MSTP14

Description

DTC module stop mode is cleared

(Initial value)

DTC module stop mode is set

7.3

Operation

7.3.1

Overview

When activated, the DTC reads register information that is already stored in memory and transfers

data on the basis of that register information. After the data transfer, it writes updated register

information back to memory. Pre-storage of register information in memory makes it possible to

transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to

perform a number of transfers with a single activation.

Figure 7.2 shows a flowchart of DTC operation.

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