HD6432142 datasheet(236/1177 Pages) RENESAS

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Section 7 Data Transfer Controller (DTC)

Rev. 4.00 Sep 27, 2006 page 192 of 1130

REJ09B0327-0400

The interrupt source flag for RXI0, for example, is the RDRF flag in SCI0.

Table 7.3

Activation Sources and DTCER Clearing

Activation

Source

When DISEL Bit Is 0 and

Specified Number of Transfers

Have Not Ended

When DISEL Bit Is 1 or

Specified Number of Transfers

Have Ended

Software

activation

SWDTE bit cleared to 0

• SWDTE bit held at 1

• Interrupt request sent to CPU

Interrupt

activation

• Corresponding DTCER bit held

at 1

• Activation source flag cleared

to 0

• Corresponding DTCER bit cleared to 0

• Activation source flag held at 1

• Activation source interrupt request

sent to CPU

Figure 7.3 shows a block diagram of activation source control. For details see section 5, Interrupt

Controller.

On-chip

supporting

module

IRQ interrupt

DTVECR

Interrupt controller

CPU

DTC

DTCER

Clear

control

Select

Interrupt

request

Source flag cleared

Clear

Clear request

Interrupt mask

Figure 7.3 Block Diagram of DTC Activation Source Control

When an interrupt has been designated a DTC activation source, existing CPU mask level and

interrupt controller priorities have no effect. If there is more than one activation source at the same

time, the DTC is activated in accordance with the default priorities.

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