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HD6432142 Scheda tecnica(PDF) 235 Page - Renesas Technology Corp |
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HD6432142 Scheda tecnica(HTML) 235 Page - Renesas Technology Corp |
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235 / 1177 page ![]() Section 7 Data Transfer Controller (DTC) Rev. 4.00 Sep 27, 2006 page 191 of 1130 REJ09B0327-0400 Table 7.2 DTC Functions Address Registers Transfer Mode Activation Source Transfer Source Transfer Destination • Normal mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 Up to 65,536 transfers possible • Repeat mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 After the specified number of transfers (1 to 256), the initial state resumes and operation continues • Block transfer mode One transfer request transfers a block of the specified size Block size is from 1 to 256 bytes or words Up to 65,536 transfers possible A block area can be designated at either the source or destination • IRQ • FRT ICI, OCI • 8-bit timer CMI • Host interface IBF • SCI TXI or RXI • A/D converter ADI • IIC IICI • Software 24 bits 24 bits 7.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software (software activation). An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. The interrupt request is directed to the DTC when the corresponding bit is set to 1, and to the CPU when the bit is cleared to 0. At the end of one data transfer (or the last of the consecutive transfers in the case of chain transfer) the interrupt source or the corresponding DTCER bit is cleared. Table 7.3 shows activation sources and DTCER clearing. |
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