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HD6432142 Scheda tecnica(PDF) 234 Page - Renesas Technology Corp |
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HD6432142 Scheda tecnica(HTML) 234 Page - Renesas Technology Corp |
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234 / 1177 page ![]() Section 7 Data Transfer Controller (DTC) Rev. 4.00 Sep 27, 2006 page 190 of 1130 REJ09B0327-0400 Start Read DTC vector Next transfer Read register information Data transfer Write register information Clear activation flag CHNE = 1? End No No Yes Yes Transfer counter = 0 or DISEL = 1? Clear DTCER Interrupt exception handling Figure 7.2 Flowchart of DTC Operation The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Table 7.2 outlines the functions of the DTC. |
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