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HD6432142 Scheda tecnica(PDF) 239 Page - Renesas Technology Corp |
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HD6432142 Scheda tecnica(HTML) 239 Page - Renesas Technology Corp |
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239 / 1177 page ![]() Section 7 Data Transfer Controller (DTC) Rev. 4.00 Sep 27, 2006 page 195 of 1130 REJ09B0327-0400 7.3.4 Location of Register Information in Address Space Figure 7.5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (vector address contents). In chain transfer, locate the register information in consecutive areas. Locate the register information in the on-chip RAM (addresses: H'FFEC00 to H'FFEFFF). Register information start address Chain transfer Register information for 2nd transfer in chain transfer MRA SAR MRB DAR CRA CRB 4 bytes Lower address CRA CRB Register information MRA 01 2 3 SAR MRB DAR Figure 7.5 Location of DTC Register Information in Address Space |
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