M32CSLASH86 datasheet(70/505 Pages) RENESAS

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Page 47

6. Voltage Detection Circuit

)

(

Low Voltage Detection Interrupt Generation Circuit

Oscillation Stop

Detection

Interrupt Signal

Watchdog Timer

NOTES:

1. Low voltage detection signal becomes "H" when the VC27 bit in the VCR2 register is set to "0" (disabled).

2. The D42 bit in the D4INT register is set to "0" (not detected) by program. The D42 bit is set to "0" when the VC27 bit is

set to "0" (low voltage detection circuit disabled).

3. The D43 bit is set to “0”(not detected) by program.

D43(3)

D41

CM10

WAIT Instruction

(Wait Mode)

D40

VC27 bit

VCC

VREF

(Rejection Range:200 ns)

VC13

Noise Rejection

Circuit

Digital

Filter

CPU

Clock

D42(2)

DF1, DF0

1/2

002

012

102

112

1/2

1/8

Noise

Rejection

Low

Voltage

Detection

Signal(1)

Underflow Signal

from the

Watchdog Timer

Low Voltage

Detection Circuit

Low Voltage

Detection

Interrupt Signal

Watchdog

Timer Interrupt

Signal

Non-

Maskable

Interrupt

Signal

Figure 6.5 Low Voltage Detection Interrupt Generation Circuit

Figure 6.6 Low Voltage Detection Interrupt Generation Circuit Operation Example

Digital Filter(2)

D42 Bit

NOTES:

1. This example applies to an operation of the low voltage detection interrupt generation circuit

when the D40 bit in the D4INT register is set to "1" (low voltage detection interrupt enabled).

2. Output from the digital filter shown in Figure 6.5.

Low Voltage

Detection

Interrupt Signal

Sampling

VC13 Bit

VCC

Sampling

No low voltage detection

interrupt signal is output

when the D42 bit is set

to "1".

Set to "0" (not detected) by program

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