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M32C/86 Scheda tecnica(PDF) 73 Page - Renesas Technology Corp |
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M32C/86 Scheda tecnica(HTML) 73 Page - Renesas Technology Corp |
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73 / 505 page ![]() Page 50 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 7. Processor Mode ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M 7.2 Setting of Processor Mode The CNVSS pin state and the PM01 and PM00 bit settings in the PM0 register determine which processor mode is selected. Table 7.2 lists processor mode after hardware reset. Table 7.3 lists processor mode selected by PM01 and PM00 bit settings. Table 7.2 Processor Mode after Hardware Reset Table 7.3 Processor Mode Selected by the PM01 and PM00 bit Settings V N C e h t o t n i l e v e L t u p n I S S n i pe d o M r o s s e c o r P V S S e d o M p i h c - e l g n i S V C C ) 2 , 1 ( e d o M r o s s e c o r p o r c i M : S E T O N g n i y l p p a n e h w , s g n i t t e s t i b 0 0 M P d n a 1 0 M P f o s s e l d r a g e r , d e s s e c c a e b t o n n a c M O R l a n r e t n i e h T . 1 V C C V N C e h t o t S S t u o - n w o r b r o 1 t e s e r e r a w d r a h ( t e s e r e r a w d r a h e h t g n i t a r e n e g d n a n i p . ) t e s e r n o i t c e t e d . s a e r a S C ll a o t d e n g i s s a e b t o n n a c s u b d e x e l p i t l u M . 2 s t i B 0 0 M P d n a 1 0 M Pe d o M r o s s e c o r P 0 0 2 e d o M p i h c - e l g n i S 1 0 2 e d o M n o i s n a p x E y r o m e M 0 1 2 e u l a v s i h t o t t e s t o n o D 1 1 2 e d o M r o s s e c o r p o r c i M If the PM01 and PM00 bits are rewritten, the mode corresponding to the PM01 and PM00 bits is selected regardless of CNVSS pin level. Do not change the PM01 and PM00 bits to "012" (memory expansion mode) or "112" (microprocessor mode) when the PM07 to PM02 bits in the PM0 register are being rewritten. Do not enter microprocessor mode while the CPU is executing a program in the internal ROM. Do not enter single-chip mode or memory expansion mode from microprocessor mode while the CPU is executing a program in an external memory space, the same address assigned for the internal ROM. The internal ROM cannot be accessed, regardless of PM01 and PM00 bit settings, when applying VCC to the CNVSS pin and generating the hardware reset (hardware reset 1 or brown-out detection reset). Figures 7.1 and 7.2 show the PM0 register and PM1 register. Figure 7.3 shows a memory map in each processor mode. |
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