3819 datasheet(39/218 Pages) RENESAS

39 / 218 page

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Internal synchronous clock selection bits

b2 b1 b0

0 0 0 : f(XIN)/8 or f(XCIN)/8

0 0 1 : f(XIN)/16 or f(XCIN)/16

0 1 0 : f(XIN)/32 or f(XCIN)/32

0 1 1 : f(XIN)/64 or f(XCIN)/64

1 1 0 : f(XIN)/128 or f(XCIN)/128

1 1 1 : f(XIN)/256 or f(XCIN)/256

Serial I/O1 port selection bit (P65, P66, and P67 V)

0 : I/O port

1 : SOUT1,SCLK11,and SCLK12 V output pins

SRDY1 output selection bit (P67)

0 : I/O port

1 : SRDY1/CS V output pin (Note)

Transfer direction selection bit

0 : LSB first

1 : MSB first

Synchronous clock selection bit

0 : External clock

1 : Internal clock

P65/SOUT1 P-channel output disable bit

0 : CMOS output (in output mode)

1 : N-channel open-drain output

(in output mode)

Serial I/O1 control register

(SIO1CON(SC1) : address 001916)

Internal synchronous clock selection bits

b2 b1 b0

0 0 0 : f(XIN)/8 or f(XCIN)/8

0 0 1 : f(XIN)/16 or f(XCIN)/16

0 1 0 : f(XIN)/32 or f(XCIN)/32

0 1 1 : f(XIN)/64 or f(XCIN)/64

1 1 0 : f(XIN)/128 or f(XCIN)/128

1 1 1 : f(XIN)/256 or f(XCIN)/256

Serial I/O2 port selection bit (P51, and P52)

0 : I/O port

1 : SOUT2 and SCLK2 output pins

SRDY2 output selection bit (P53)

0 : I/O port

1 : SRDY2 output pin

Transfer direction selection bit

0 : LSB first

1 : MSB first

Synchronous clock selection bit

0 : External clock

1 : Internal clock

P51/SOUT2 P-channel output disable bit

0 : CMOS output (in output mode)

1 : N-channel open-drain output

(in output mode)

Serial I/O2 control register

(SIO2CON(SC2) : address 001D16)

Internal synchronous clock selection bits

b2 b1 b0

0 0 0 : f(XIN)/8 or f(XCIN)/8

0 0 1 : f(XIN)/16 or f(XCIN)/16

0 1 0 : f(XIN)/32 or f(XCIN)/32

0 1 1 : f(XIN)/64 or f(XCIN)/64

1 1 0 : f(XIN)/128 or f(XCIN)/128

1 1 1 : f(XIN)/256 or f(XCIN)/256

Serial I/O3 port selection bit (P55 and P56)

0 : I/O port

1 : SOUT3 and SCLK3 output pins

SRDY3 output selection bit (P57)

0 : I/O port

1 : SRDY3 and SCLK3 output pins

Transfer direction selection bit

0 : LSB first

1 : MSB first

Synchronous clock selection bit

0 : External clock

1 : Internal clock

P55/SOUT3 P-channel output disable bit

0 : CMOS output (in output mode)

1 : N-channel open-drain output

(in output mode)

Serial I/O3 control register

(SIO3CON(SC3) : address 001E16)

V : Valid only in serial I/O automatic transfer mode.

Note: When the external clock is selected in the serial I/O1 automatic transfer mode, the SRDY1 signal pin becomes the CS signal input pin.

Fig. 14 Structure of serial I/O control registers

3819 Scheda tecnica(PDF) 39 Page - Renesas Technology Corp

3819 Scheda tecnica(HTML) 39 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL