3819 datasheet(33/218 Pages) RENESAS

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3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

TIMERS

The 3819 group has 6 built-in timers: timer 1, timer 2, timer 3,

timer 4, timer 5, and timer 6.

Each timer has the 8-bit timer latch. The timers count down.

Once a timer reaches 0016, at the next count pulse the contents of

each timer latch is loaded into the corresponding timer, and sets

the corresponding interrupt request bit to “1”.

The count can be stopped by setting the stop bit of each timer to

“1”. The internal clock

φ can be set to either the high-speed mode

or low-speed mode with the CPU mode register. At the same time,

timer internal count source is switched to either f(XIN) or f(XCIN).

Timer 1 and Timer 2

The count sources of timer 1 and timer 2 can be selected by set-

ting the timer 12 mode register. A rectangular waveform of timer 1

underflow signal divided by 2 is output from the P46/T1OUT pin.

The waveform polarity changes each time timer 1 overflows. The

active edge of the external clock CNTR0 can be switched with the

bit 6 of the interrupt edge selection register.

At reset or when executing the STP instruction, all bits of the timer

12 mode register are cleared to “0”, timer 1 is set to “FF16”, and

timer 2 is set to “0116”.

Timer 3 and Timer 4

The count sources of timer 3 and timer 4 can be selected by set-

ting the timer 34 mode register. A rectangular waveform of timer 3

underflow signal divided by 2 is output from the P47/T3OUT pin.

The waveform polarity changes each time timer 3 overflows.

The active edge of the external clock CNTR1 can be switched with

the bit 7 of the interrupt edge selection register.

Timer 5 and Timer 6

The count sources of timer 5 and timer 6 can be selected by set-

ting the timer 56 mode register.

A rectangular waveform of timer 6 underflow signal divided by 2 is

output from the P61/PWM pin. The waveform polarity changes

each time timer 6 overflows.

Timer 6 PWM Mode

Timer 6 can output a rectangular waveform with duty cycle n/(n +

m) from the P61/PWM pin by setting the timer 56 mode register

(refer to fig. 12). The n is the value set in timer 6 latch (address

002516) and m is the value in the timer 6 PWM register (address

002716). If n is “0”, the PWM output is “L”, if m is “0”, the PWM out-

put is “H”(n=0 is prior than m=0). In the PWM mode, interrupts

occur at the rising edge of the PWM output.

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