3819 datasheet(80/218 Pages) RENESAS

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3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Timing after interrupt

The interrupt processing routine begins with the machine cycle following the completion of the instruction that is

currently in execution.

Figure 61 shows a timing chart after an interrupt occurs, and figure 62 shows the time up to execution of the interrupt

processing routine.

Fig. 61 Timing chart after an interrupt occurs

Fig. 62 Time up to execution of the interrupt processing routine

: CPU operation code fetch cycle

(This is an internal signal which cannot be observed from the external unit.)

: Vector address of each interrupt

: Jump destination address of each interrupt

: “0016” or “0116”

SYNC

BL, BH

AL, AH

SPS

Generation of interrupt request

Main routine

Interrupt processing routine

7 to 23 cycles

(At performing 8.4 MHz, 1.7

µs to 5.5 µs)

2 cycles

5 cycles

Start of interrupt processing

0 to 16* cycles

* : at execution of DIV instruction

Waiting time for

post-processing

of pipeline

Stack push and

Vector fetch

Data bus

Not used

PCH

PCL

Address bus

S, SPS

S-2, SPS

S-1, SPS

AL, AH

SYNC

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