AD9548SLASHPCBZ datasheet(48/112 Pages) AD

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AD9548

Rev. 0 | Page 48 of 112

special because it represents the null condition (see the

EEPROM Conditional Processing section).

A pause instruction, like an end instruction, is stored at the end

of a sequence of instructions in the scratch pad. When the

controller encounters a pause instruction during an upload

sequence, it keeps the EEPROM address pointer at its last value.

This way the user can store a new instruction sequence in the

scratch pad and upload the new sequence to the EEPROM. The

new sequence is stored in the EEPROM address locations

immediately following the previously saved sequence. This

process is repeatable until an upload sequence contains an end

instruction. The pause instruction is also useful when used in

conjunction with condition processing. It allows the EEPROM

to contain multiple occurrences of the same register(s), with

each occurrence linked to a set of conditions (see the EEPROM

Conditional Processing section).

EEPROM Upload

To upload data to the EEPROM, the user must first ensure that

the write enable bit (Register 0E00, Bit 0) is set. Then, on setting

the autoclearing save to EEPROM bit (Register 0E02, Bit 0), the

controller initiates the EEPROM data storage process.

Uploading EEPROM data requires that the user first write an

instruction sequence into the scratch pad registers. During the

upload process, the controller reads the scratch pad data byte by

byte, starting at Register 0E10 and incrementing the scratch pad

address pointer as it goes until it reaches a pause or End

instruction.

As the controller reads the scratch pad data, it transfers the data

from the scratch pad to the EEPROM (byte by byte) and

increments the EEPROM address pointer accordingly, unless it

encounters a data instruction. A data instruction tells the

controller to transfer data from the device settings portion of

the register map to the EEPROM. The number of bytes to

transfer is encoded within the data instruction, and the starting

address for the transfer appears in the next two bytes in the

scratch pad.

When the controller encounters a data instruction, it stores the

instruction in the EEPROM, increments the EEPROM address

pointer, decodes the number of bytes to be transferred, and

increments the scratch pad address pointer. Then it retrieves the

next two bytes from the scratch pad (the target address) and

increments the scratch pad address pointer by 2. Next, the

controller transfers the specified number of bytes from the

When it completes the data transfer, the controller stores an

extra byte in the EEPROM to serve as a checksum for the

transferred block of data. To account for the checksum byte, the

controller increments the EEPROM address pointer by one

more than the number of bytes transferred. Note that, when the

controller transfers data associated with an active register, it

actually transfers the buffered contents of the register (see the

Buffered/Active Registers section for details on the difference

between buffered and active registers). This allows for the transfer

of nonzero autoclearing register contents.

Note that conditional processing (see the EEPROM Conditional

Processing section) does not occur during an upload sequence.

EEPROM Download

An EEPROM download results in data transfer from the

EEPROM to the device register map. To download data, the

user sets the autoclearing load from EEPROM bit (Register

0E03, Bit 1). This commands the controller to initiate the

EEPROM download process. During download, the controller

reads the EEPROM data byte by byte, incrementing the

EEPROM address pointer as it goes, until it reaches an end

instruction. As the controller reads the EEPROM data, it

executes the stored instructions, which includes transferring

stored data to the device settings portion of the register map

whenever it encounters a data instruction.

Note that conditional processing (see the EEPROM Conditional

Processing section) is only applicable when downloading.

Automatic EEPROM Download

Following a power-up, an assertion of the RESET pin, or a soft

reset (Register 0000, Bit 5 = 1), if FncInit[7:3] ≠ 0 (see the Initial

Pin Programming section), then the instruction sequence

stored in the EEPROM executes automatically with condition =

FncInit[7:3]. In this way, a previously stored set of register values

downloads automatically on power-up or with a hard or soft

reset. See the EEPROM Conditional Processing section for

details regarding conditional processing and the way it modifies

the download process.

EEPROM Conditional Processing

The condition instructions allow conditional execution of

EEPROM instructions during a download sequence. During

an upload sequence, however, they are stored as is and have

no effect on the upload process.

Note that, during EEPROM downloads, the condition instructions

themselves and the end instruction always execute unconditionally.

Conditional processing makes use of two elements: the condition

(from Condition 1 to Condition 31) and the condition tag

board. The relationships among the condition, the condition tag

board, and the EEPROM controller appear schematically in

Figure 50.

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