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AD9548/PCBZ Scheda tecnica(PDF) 57 Page - Analog Devices

Il numero della parte AD9548/PCBZ
Spiegazioni elettronici  Quad/Octal Input Network Clock Generator/Synchronizer
PDF  112 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
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AD9548/PCBZ Scheda tecnica(HTML) 57 Page - Analog Devices

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AD9548
Rev. 0 | Page 57 of 112
Data Transfer Format
Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.
S
Slave
address
W
A
RAM address
high byte
A
RAM address
low byte
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
P
Send byte format—the send byte protocol is used to set up the register address for subsequent reads.
S
Slave address
W
A
RAM address high byte
A
RAM address low byte
A
P
Receive byte format—the receive byte protocol is used to read the data byte(s) from RAM starting from the current address.
S
Slave address
R
A
RAM Data 0
A
RAM Data 1
A
RAM Data 2
A
P
Read byte format—the combined format of the send byte and the receive byte.
S
Slave
Address
W
A
RAM
Address
High Byte
A
RAM
Address
Low Byte
A
Sr
Slave
Address
R
A
RAM
Data
0
A
RAM
Data
1
A
RAM
Data
2
A
P
I²C Serial Port Timing
SSr
P
S
SDA
SCL
tSP
tHD; STA
tSU; STA
tSU; DAT
tHD; DAT
tHD; STA
tHI
tLO
tSU; STO
tBUF
tR
tF
tR
tF
Figure 64. I²C Serial Port Timing
Table 34. I2C Timing Definitions
Parameter
Description
fSCL
Serial clock
tBUF
Bus free time between stop and start conditions
tHD; STA
Repeated hold time start condition
tSU; STA
Repeated start condition setup time
tSU; STO
Stop condition setup time
tHD; DAT
Data hold time
tSU; DAT
Date setup time
tLO
SCL clock low period
tHI
SCL clock high period
tR
Minimum/maximum receive SCL and SDA rise time
tF
Minimum/maximum receive SCL and SDA fall time
tSP
Pulse width of voltage spikes that must be suppressed by the input filter



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