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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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AD9548/PCBZ Scheda tecnica(PDF) 81 Page - Analog Devices |
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AD9548/PCBZ Scheda tecnica(HTML) 81 Page - Analog Devices |
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81 / 112 page  AD9548 Rev. 0 | Page 81 of 112 Table 73. Q3 Divider1 Address Bits Bit Name Description 0414 [7:0] Q3 Q3 divider, Bits[7:0] 0415 [7:0] Q3 divider, Bits[15:8] 0416 [7:0] Q3 divider, Bits[23:16] 0417 [7:6] Unused [5:0] Q3 Q3 divider, Bits[29:24] 1 The default value is 0 (or divide by 1). REFERENCE INPUT CONFIGURATION (REGISTER 0500 TO REGISTER 0507) Table 74. Reference Power-Down When all bits are set, the reference receiver section enters a deep sleep mode. Address Bits Bit Name Description 0500 [7] Ref DD power-down REF DD input receiver power-down 0 (default) = normal operation 1 = power-down [6] Ref D power-down REF D input receiver power-down 0 (default) = normal operation 1 = power-down [5] Ref CC power-down REF CC input receiver power-down 0 (default) = normal operation 1 = power-down [4] Ref C power-down REF C input receiver power-down 0 (default) = normal operation 1 = power-down [3] Ref BB power-down REF BB input receiver power-down 0 (default) = normal operation 1 = power-down [2] Ref B power-down REF B input receiver power-down 0 (default) = normal operation 1 = power-down [1] Ref AA power-down REF AA input receiver power-down 0 (default) = normal operation 1 = power-down [0] Ref A power-down REF A input receiver power-down 0 (default) = normal operation 1 = power-down |
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