AD9548SLASHPCBZ datasheet(102/112 Pages) AD

102 / 112 page

AD9548

Rev. 0 | Page 102 of 112

Table 145. EEPROM Storage Sequence for Clock Distribution Settings

Address

Bits

Bit Name

Description

0E1B

[7:0]

Clock distribution

The default value of this register is 0x19, which the controller interprets as a data

instruction. Its decimal value is 25, which tells the controller to transfer 26 bytes of

data (25 + 1) beginning at the address specified by the next two bytes. The controller

stores 0x19 in the EEPROM and increments the EEPROM address pointer.

0E1C

[7:0]

Clock distribution

The default value of these two registers is 0x0400. Note that Register 0E1C and

address, respectively. Because the previous register contains a data instruction, these

two registers define a starting address (in this case, 0x0400). The controller stores

0x0400 in the EEPROM and increments the EEPROM pointer by 2. It then transfers

26 bytes from the register map (beginning at Address 0x0400) to the EEPROM and

increments the EEPROM address pointer by 27 (26 data bytes and one checksum

byte). The 26 bytes transferred correspond to the clock distribution parameters in the

0E1D

[7:0]

0E1E

[7:0]

I/O update

The default value of this register is 0x80, which the controller interprets as an I/O

update instruction. The controller stores 0x80 in the EEPROM and increments the

EEPROM address pointer.

Table 146. EEPROM Storage Sequence for Reference Input Settings

Address

Bits

Bit Name

Description

0E1F

[7:0]

Reference inputs

The default value of this register is 0x07, which the controller interprets as a data

instruction. Its decimal value is 7, which tells the controller to transfer eight bytes of

data (7 + 1) beginning at the address specified by the next two bytes. The controller

stores 0x07 in the EEPROM and increments the EEPROM address pointer.

0E20

[7:0]

Reference inputs

The default value of these two registers is 0x0500. Note that Register 0E20 and

address, respectively. Because the previous register contains a data instruction,

these two registers define a starting address (in this case, 0x0500). The controller

stores 0x0500 in the EEPROM and increments the EEPROM pointer by 2. It then

transfers eight bytes from the register map (beginning at Address 0x0500) to the

EEPROM and increments the EEPROM address pointer by nine (eight data bytes and

one checksum byte). The eight bytes transferred correspond to the reference inputs

parameters in the register map.

0E21

[7:0]

Table 147. EEPROM Storage Sequence for Profile 0 and Profile 1 Settings

Address

Bits

Bit Name

Description

0E22

[7:0]

Profile 0 and Profile 1

The default value of this register is 0x63, which the controller interprets as a data

instruction. Its decimal value is 99, which this tells the controller to transfer 100 bytes

of data (99 + 1) beginning at the address specified by the next two bytes. The

controller stores 0x63 in the EEPROM and increments the EEPROM address pointer.

0E23

[7:0]

Profile 0 and Profile 1

The default value of these two registers is 0x0600. Note that Register 0E23 and

address, respectively. Because the previous register contains a data instruction,

these two registers define a starting address (in this case, 0x0600). The controller

stores 0x0600 in the EEPROM and increments the EEPROM pointer by 2. It then

transfers 100 bytes from the register map (beginning at Address 0x0600) to the

EEPROM and increments the EEPROM address pointer by 101 (100 data bytes and

one checksum byte). The 99 bytes transferred correspond to the Profile 0 and

Profile 1 parameters in the register map.

0E24

[7:0]

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