ATmega162 datasheet(19/324 Pages) ATMEL

19 / 324 page

2513K–AVR–07/09

ATmega162/V

Figure 9. Data Memory Map

Data Memory Access

Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk

CPU cycles as described in Figure 10.

Figure 10. On-chip Data SRAM Access Cycles

EEPROM Data

Memory

The ATmega162 contains 512 bytes of data EEPROM memory. It is organized as a separate

data space, in which single bytes can be read and written. The EEPROM has an endurance of at

least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described

in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and

the EEPROM Control Register.

32 Registers

64 I/O Registers

Internal SRAM

(1024 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x0460

0x045F

0xFFFF

0x0060

Data Memory

External SRAM

(0 - 64K x 8)

Memory configuration B

32 Registers

64 I/O Registers

Internal SRAM

(1024 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x04FF

0xFFFF

0x0060 - 0x00FF

Data Memory

External SRAM

(0 - 64K x 8)

Memory configuration A

160 Ext I/O Reg.

0x0100

0x0500

clk

Data

Address

Address valid

Compute Address

CPU

Memory Access Instruction

Next Instruction

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