ATmega162 datasheet(41/324 Pages) ATMEL

41 / 324 page

2513K–AVR–07/09

ATmega162/V

grammed. Any clock sources, including Internal RC Oscillator, can be selected when PortB 0

serves as clock output.

If the system clock prescaler is used, it is the divided system clock that is output when the

CKOUT Fuse is programmed. See “System Clock Prescaler” on page 41. for a description of the

system clock prescaler.

Timer/Counter

Oscillator

For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is

connected directly between the pins. The Oscillator provides internal capacitors on TOSC1 and

TOSC2, thereby removing the need for external capacitors. The internal capacitors have a nom-

inal value of 10 pF. The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying

an external clock source to TOSC1 is not recommended.

System Clock

Prescaler

The ATmega162 system clock can be divided by setting the Clock Prescale Register – CLKPR.

This feature can be used to decrease the system clock frequency and power consumption when

the requirement for processing power is low. This can be used with all clock source options, and

it will affect the clock frequency of the CPU and all synchronous peripherals. clk

I/O, clkCPU, and

clk

FLASH are divided by a factor as shown in Table 15. Note that the clock frequency of clkASY

(asynchronously Timer/Counter) only will be scaled if the Timer/Counter is clocked

synchronously.

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occur in the clock system and that no intermediate frequency is higher than neither the

clock frequency corresponding to the previous setting, nor the clock frequency corresponding to

the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock,

which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the

state of the prescaler – even if it were readable, and the exact time it takes to switch from one

clock division to another cannot be exactly predicted.

From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the

new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the

previous clock period, and T2 is the period corresponding to the new prescaler setting.

To avoid unintentional changes of clock frequency, a special write procedure must be followed

to change the CLKPS bits:

Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in

CLKPR to zero.

Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Caution: An interrupt between step 1 and step 2 will make the timed sequence fail. It is recom-

mended to have the Global Interrupt Flag cleared during these steps to avoid this problem.

Clock Prescale

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. CLKPCE is

cleared by hardware four cycles after it is written or when CLKPS is written. Setting the CLKPCE

bit will disable interrupts, as explained in the CLKPS description below.

Bit

CLKPCE

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

CLKPR

Read/Write

R/W

Initial Value

See Bit Description

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