ATmega162 datasheet(27/324 Pages) ATMEL

27 / 324 page

2513K–AVR–07/09

ATmega162/V

The control bits for the External Memory Interface are located in three registers, the MCU Con-

trol Register – MCUCR, the Extended MCU Control Register – EMCUCR, and the Special

Function IO Register – SFIOR.

When the XMEM interface is enabled, it will override the settings in the Data Direction registers

corresponding to the ports dedicated to the interface. For details about this port override, see the

alternate functions in section “I/O-Ports” on page 63. The XMEM interface will autodetect

whether an access is internal or external. If the access is external, the XMEM interface will out-

put address, data, and the control signals on the ports according to Figure 13 (this figure shows

the wave forms without wait-states). When ALE goes from high to low, there is a valid address

on AD7:0. ALE is low during a data transfer. When the XMEM interface is enabled, also an inter-

nal access will cause activity on address-, data- and ALE ports, but the RD and WR strobes will

not toggle during internal access. When the External Memory Interface is disabled, the normal

pin and data direction settings are used. Note that when the XMEM interface is disabled, the

address space above the internal SRAM boundary is not mapped into the internal SRAM. Figure

12 illustrates how to connect an external SRAM to the AVR using an octal latch (typically

“74x573” or equivalent) which is transparent when G is high.

Address Latch

Requirements

Due to the high-speed operation of the XRAM interface, the address latch must be selected with

care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at condi-

tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The

external memory interface is designed in compliance to the 74AHC series latch. However, most

latches can be used as long they comply with the main timing parameters. The main parameters

for the address latch are:

•

D to Q propagation delay (t

pd).

•

Data setup time before G low (t

su).

•

Data (address) hold time after G low (

th).

The external memory interface is designed to guaranty minimum address hold time after G is

asserted low of t

h = 5 ns (refer to tLAXX_LD/tLLAXX_ST in Table 114 to Table 121 on page 272). The

D to Q propagation delay (t

pd) must be taken into consideration when calculating the access time

requirement of the external component. The data setup time before G low (t

su) must not exceed

address valid to ALE low (t

AVLLC) minus PCB wiring delay (dependent on the capacitive load).

Figure 12. External SRAM Connected to the AVR

D[7:0]

A[7:0]

A[15:8]

SRAM

AD7:0

ALE

A15:8

AVR

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