PCF8533USLASH2SLASHF2 datasheet(22/45 Pages) NXP

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PCF8533_4

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Product data sheet

Rev. 04 — 5 March 2010

22 of 45

NXP Semiconductors

PCF8533

Universal LCD driver for low multiplex rates

The acknowledgement after each byte is made only by the (A0, A1, and A2) addressed

PCF8533. After the last (display) byte, the I2C-bus master asserts a STOP condition (P).

Alternatively a START may be asserted to RESTART an I2C-bus access.

8.2 Command decoder

The command decoder identifies command bytes that arrive on the I2C-bus. The five

commands available to the PCF8533 are defined in Table 9.

Table 9.

Definition of commands

Command

Operation code

Reference

mode-set

Table 10

load-data-pointer

P4P3P2P1P0

Table 11

device-select

Table 12

bank-select

Table 13

blink-select

BF1

BF0

Table 14

Table 10.

Mode-set command bit description

Bit

Symbol

Value

Description

7 to 4

1100

fixed value

display status

the possibility to disable the display allows implementation of

blinking under external control

disabled (blank)

enabled

LCD bias configuration

⁄

3 bias

⁄

2 bias

1 to 0

M[1:0]

LCD drive mode selection

static; 1 backplane

1:2 multiplex; 2 backplanes

1:3 multiplex; 3 backplanes

1:4 multiplex; 4 backplanes

Table 11.

Load-data-pointer command bit description

See Section 7.11.

Bit

Symbol

Value

Description

fixed value

6 to 0

P[6:0]

0000000 to

1001111

immediate data

7-bit binary value of 0 to 79, transferred to the data pointer to

define one of 80 display RAM addresses

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