PCF8533USLASH2SLASHF2 datasheet(32/45 Pages) NXP

32 / 45 page

PCF8533_4

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Product data sheet

Rev. 04 — 5 March 2010

32 of 45

NXP Semiconductors

PCF8533

Universal LCD driver for low multiplex rates

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCF8533s. This synchronization is guaranteed after the power-on reset. The only time

that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in

adverse electrical environments, or by the definition of a multiplex mode when PCF8533s

with different SA0 levels are cascaded).

SYNC is organized as an input/output pin; the output selection being realized as an

open-drain driver with an internal pull-up resistor. A PCF8533 asserts the SYNC line at the

onset of its last active backplane signal and monitors the SYNC line at all other times.

Should synchronization in the cascade be lost, it will be restored by the first PCF8533 to

assert SYNC. The timing relationships between the backplane waveforms and the SYNC

signal for the various drive modes of the PCF8533 are shown in Figure 23.

Fig 22. Cascaded PCF8533 configuration

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

SDA

SCL

CLK

OSC

SYNC

80 segment drives

4 backplanes

80 segment drives

LCD PANEL

(up to 5120

elements)

PCF8533

SA0

VSS

VDD

VLCD

VDD

VLCD

mgl754

SDA

SDAACK

SCL

SYNC

CLK

OSC

BP0 to BP3

(open-circuit)

SA0

PCF8533

BP0 to BP3

2Cb

≤

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