PIC12F629-ISLASHSN datasheet(26/136 Pages) MICROCHIP

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PIC12F629/675

DS41190G-page 26

 2010 Microchip Technology Inc.

3.3.5

GP4/AN3/T1G/OSC2/CLKOUT

Figure 3-4 shows the diagram for this pin. The GP4 pin

is configurable to function as one of the following:

• a general purpose I/O

• an analog input for the A/D (PIC12F675 only)

• a TMR1 gate input

• a crystal/resonator connection

• a clock output

FIGURE 3-4:

BLOCK DIAGRAM OF GP4

3.3.6

GP5/T1CKI/OSC1/CLKIN

Figure 3-5 shows the diagram for this pin. The GP5 pin

is configurable to function as one of the following:

• a general purpose I/O

•a TMR1 clock input

• a crystal/resonator connection

• a clock input

FIGURE 3-5:

BLOCK DIAGRAM OF GP5

I/O pin

VDD

VSS

VDD

Weak

Analog

Input Mode

Data Bus

WPU

PORT

TRISIO

IOC

Interrupt-on-Change

FOSC/4

To A/D Converter

Oscillator

Circuit

OSC1

CLKOUT

Enable

Analog

Input Mode

GPPU

RD PORT

To TMR1 T1G

INTOSC/

RC/EC(2)

CLK

Modes(1)

CLKOUT

Enable

Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT

Enable.

2: With CLKOUT option.

I/O pin

VDD

VSS

VDD

Weak

Data Bus

WPU

PORT

TRISIO

IOC

Interrupt-on-Change

To TMR1 or CLKGEN

INTOSC

Mode

RD PORT

INTOSC

Mode

GPPU

Oscillator

Circuit

OSC2

Note

1: Timer1 LP Oscillator enabled

2: When using Timer1 with LP oscillator, the Schmitt

Trigger is by-passed.

(2)

TMR1LPEN(1)

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