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PIC12F629-I/SN Scheda tecnica(PDF) 32 Page - Microchip Technology |
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PIC12F629-I/SN Scheda tecnica(HTML) 32 Page - Microchip Technology |
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32 / 136 page ![]() PIC12F629/675 DS41190G-page 32 2010 Microchip Technology Inc. 5.0 TIMER1 MODULE WITH GATE CONTROL The PIC12F629/675 devices have a 16-bit timer. Figure 5-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: • 16-bit timer/counter (TMR1H:TMR1L) • Readable and writable • Internal or external clock selection • Synchronous or asynchronous operation • Interrupt on overflow from FFFFh to 0000h • Wake-up upon overflow (Asynchronous mode) • Optional external enable input (T1G) • Optional LP oscillator The Timer1 Control register (T1CON), shown in Register 5.1, is used to enable/disable Timer1 and select the various features of the Timer1 module. FIGURE 5-1: TIMER1 BLOCK DIAGRAM Note: Additional information on timer modules is available in the PIC® Mid-Range Refer- ence Manual, (DS33023). TMR1H TMR1L LP Oscillator T1SYNC TMR1CS T1CKPS<1:0> Sleep Input FOSC/4 Internal Clock Prescaler 1, 2, 4, 8 Synchronize Detect 1 0 0 1 Synchronized Clock Input 2 OSC1 OSC2 Set Flag bit TMR1IF on Overflow TMR1 TMR1ON TMR1GE TMR1ON TMR1GE INTOSC T1OSCEN LP w/o CLKOUT T1G |
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