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PIC12F629-I/SN Scheda tecnica(PDF) 74 Page - Microchip Technology

Il numero della parte PIC12F629-I/SN
Spiegazioni elettronici  8-Pin, Flash-Based 8-Bit CMOS Microcontrollers
PDF  136 Pages
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Produttore elettronici  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC12F629-I/SN Scheda tecnica(HTML) 74 Page - Microchip Technology

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PIC12F629/675
DS41190G-page 74
 2010 Microchip Technology Inc.
BTFSC
Bit Test, Skip if Clear
Syntax:
[label] BTFSC f,b
Operands:
0
 f  127
0
 b  7
Operation:
skip if (f<b>) = 0
Status Affected:
None
Description:
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the
next instruction is discarded, and
a NOP is executed instead, making
this a 2TCY instruction.
CALL
Call Subroutine
Syntax:
[ label ] CALL k
Operands:
0
 k  2047
Operation:
(PC)+ 1
 TOS,
k
 PC<10:0>,
(PCLATH<4:3>)
 PC<12:11>
Status Affected:
None
Description:
Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL is
a two-cycle instruction.
CLRF
Clear f
Syntax:
[label] CLRF f
Operands:
0
 f  127
Operation:
00h
 (f)
1
 Z
Status Affected:
Z
Description:
The contents of register ‘f’ are
cleared and the Z bit is set.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h
 (W)
1
 Z
Status Affected:
Z
Description:
W register is cleared. Zero bit (Z)
is set.
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRWDT
Operands:
None
Operation:
00h
 WDT
0
 WDT prescaler,
1
 TO
1
 PD
Status Affected:
TO, PD
Description:
CLRWDT
instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT.
Status bits TO and PD are set.
COMF
Complement f
Syntax:
[ label ] COMF f,d
Operands:
0
 f  127
d
 [0,1]
Operation:
(f)
 (destination)
Status Affected:
Z
Description:
The contents of register ‘f’ are
complemented. If ‘d’ is 0, the
result is stored in W. If ‘d’ is 1, the
result is stored back in register ‘f’.
DECF
Decrement f
Syntax:
[label] DECF f,d
Operands:
0
 f  127
d
 [0,1]
Operation:
(f) - 1
 (destination)
Status Affected:
Z
Description:
Decrement register ‘f’. If ‘d’ is 0,
the result is stored in the W
register. If ‘d’ is 1, the result is
stored back in register ‘f’.



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