PIC12F629-ISLASHSN datasheet(42/136 Pages) MICROCHIP

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PIC12F629/675

DS41190G-page 42

 2010 Microchip Technology Inc.

VRCON: VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)

6.9

Comparator Interrupts

The comparator interrupt flag is set whenever there is

a change in the output value of the comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON<6>, to

determine the actual change that has occurred. The

CMIF bit, PIR1<3>, is the comparator interrupt flag.

This bit must be reset in software by clearing it to ‘0’.

Since it is also possible to write a ‘1’ to this register, a

simulated interrupt may be initiated.

The CMIE bit (PIE1<3>) and the PEIE bit (INT-

CON<6>) must be set to enable the interrupt. In addi-

tion, the GIE bit must also be set. If any of these bits are

cleared, the interrupt is not enabled, though the CMIF

bit will still be set if an interrupt condition occurs.

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

a) Any read or write of CMCON. This will end the

mismatch condition.

b) Clear flag bit CMIF.

A mismatch condition will continue to set flag bit CMIF.

Reading CMCON will end the mismatch condition, and

allow flag bit CMIF to be cleared.

TABLE 6-2:

REGISTERS ASSOCIATED WITH COMPARATOR MODULE

R/W-0

U-0

R/W-0

VREN

—VRR

—VR3

VR2

VR1

VR0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

VREN: CVREF Enable bit

1 = CVREF circuit powered on

0 = CVREF circuit powered down, no IDD drain

bit 6

Unimplemented: Read as ‘0’

bit 5

VRR: CVREF Range Selection bit

= Low range

= High range

bit 4

Unimplemented: Read as ‘0’

bit 3-0

VR3:VR0: CVREF value selection 0

 VR [3:0]  15

When VRR = 1: CVREF = (VR3:VR0 / 24) * VDD

When VRR = 0: CVREF = VDD/4 + (VR3:VR0 / 32) * VDD

Note:

If a change in the CMCON register (COUT)

should occur when a read operation is

being executed (start of the Q2 cycle), then

the CMIF (PIR1<3>) interrupt flag may not

get set.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOD

Value on

all other

Resets

0Bh/8Bh

INTCON

GIE

PEIE

T0IE

INTE

GPIE

T0IF

INTF

GPIF

0000 0000

0000 000u

0Ch

PIR1

EEIF

ADIF

—

—CMIF

—

TMR1IF

00-- 0--0

19h

CMCON

—COUT

—

CINV

CIS

CM2

CM1

CM0

-0-0 0000

8Ch

PIE1

EEIE

ADIE

—

—CMIE

—

TMR1IE

00-- 0--0

85h

TRISIO

—

TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111

--11 1111

99h

VRCON

VREN

—VRR

—

VR3

VR2

VR1

VR0

0-0- 0000

Legend:

x = unknown, u = unchanged, - = unimplemented, read as ‘

0’. Shaded cells are not used by the comparator module.

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