MPC8378E datasheet(26/127 Pages) FREESCALE

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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

Output differential voltage 2, 3, 5

|VOD|

323

500

725

Equalization

setting: 1.0

296

459

665

Equalization

setting: 1.09

269

417

604

Equalization

setting: 1.2

243

376

545

Equalization

setting: 1.33

215

333

483

Equalization

setting: 1.5

189

292

424

Equalization

setting: 1.71

162

250

362

Equalization

setting: 2.0

Output offset voltage

VOS

425

500

575

1, 4

Output impedance

(single-ended)

—

Mismatch in a pair

——

—

Change in VOD between “0” and

“1”

|VOD|—

—

Change in VOS between “0” and

“1”

VOS

——

—

Output current on short to GND

ISA, ISB

——

—

Note:

1 This will not align to DC-coupled SGMII. XV

DD_SRDS-Typ =1.0 V.

2 |V

OD|=|VSD_TXn -VSD_TXn|. |VOD| is also referred as output differential peak voltage. VTX-DIFFp-p =2 × |VOD|.

3 The |V

OD| value shown in the table assumes the following transmit equalization setting in SRDSnCR0[DDPA] and

SRDSnCR0[TXEQA] for lane A, and SRDSnCR0[DDPE] and SRDSnCR0[TXEQE] for lane E.

•

DPPA or DPPE bit is set to zero (selecting the full VDD-DIFF-p-p amplitude – power up default);

•

TXEQA or TXDQE is set based on the equalization setting shown in table.

4 V

OS is also referred to as output common mode voltage.

5 The |V

OD| value shown in the Typ column is based on the condition of XVDD_SRDS-Typ = 1.0 V, no common mode offset

variation (VOS = 500 mV), SerDes1 transmitter is terminated with 100-Ω differential load between SD_TXn and SD_TXn.

Table 27. SGMII DC Receiver Electrical Characteristics

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Supply voltage

(L1_SDAVDD_0, L1_XCOREVDD)

XVDD_SRDS

0.95

1.0

1.05

—

DC input voltage range

—

N/A

—

Table 26. SGMII DC Transmitter Electrical Characteristics (continued)

Parameter

Symbol

Min

Typ

Max

Unit

Notes

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