MPC8378E datasheet(20/127 Pages) FREESCALE

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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

DDR1 and DDR2 SDRAM

The minimum frequency for DDR2 is 250 MHz data rate (125 MHz clock), 167 MHz data rate (83 MHz

clock) for DDR1.

MDQ//MDM output setup with respect to MDQS

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate

tDDKHDS,

tDDKLDS

550

800

1100

1200

—

5, 8

MDQ//MDM output hold with respect to MDQS

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate

tDDKHDX,

tDDKLDX

700

800

1100

1200

—

5, 8

MDQS preamble start

tDDKHMP

–0.5

× t

MCK –0.6

–0.5

× t

MCK + 0.6

6, 8

MDQS epilogue end

tDDKHME

–0.6

0.6

6, 8

Note:

1 The symbols used for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2 All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3 ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.

4 Note that t

DDKHMH follows the symbol conventions described in Note 1. For example, tDDKHMH describes the DDR timing (DD)

from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control

of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in

the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same

adjustment value. See the MPC8379E PowerQUICC II Pro Host Processor Reference Manual for a description and

understanding of the timing modifications enabled by use of these bits.

5 Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data MDQ, ECC, or

data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6 All outputs are referenced to the rising edge of MCKn at the pins of the microprocessor. Note that t

DDKHMP follows the symbol

conventions described in Note 1.

7 Clock Control register is set to adjust the memory clocks by 1/2 the applied cycle.

8 See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.

Table 21. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued)

Parameter

Symbol1

Min

Max

Unit

Notes

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