MPC8378E datasheet(27/127 Pages) FREESCALE

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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

Figure 8. SGMII Transmitter DC Measurement Circuit

8.2.3

DC Requirements for SGMII SD_REF_CLK and SD_REF_CLK_B

See Section 20.2.2, “DC Level Requirement for SerDes Reference Clocks.”

8.3

SGMII, MII, RGMII, RMII, and RTBI AC Timing Specifications

The AC timing specifications for SGMII, MII, RGMII, RMII, and RTBI are presented in this section.

Input differential voltage

SEICx = 01

SEICx = 00

VRX_DIFFp-p

100

175

—1200

2, 4

Loss of signal threshold

SEICx = 01

SEICx = 00

VLOS

—

100

175

3, 4

Input AC common mode voltage

VCM_ACp-p

—

100

Receiver differential input

impedance

ZRX_DIFF

100

120

—

Receiver common mode input

impedance

ZRX_CM

—

Common mode input voltage

VCM

—Vxcorevss

—V

Note:

1 Input must be externally AC-coupled.

2 V

RX_DIFFp-p is also referred to as peak to peak input differential voltage.

3 The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in PCI Express. Refer to PCI

Express Differential Receiver (RX) Input Specifications section for further explanation.

4 The SEICx shown in the table refers to SRDSnCR[SEICA] for lane A and SRDSnCR[SEICE] for lane E.

5 V

CM_ACp-p is also referred to as peak to peak AC common mode voltage.

6 On-chip termination to SGND_SRDSn (xcorevss).

Table 27. SGMII DC Receiver Electrical Characteristics (continued)

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Transmitter

L1_SD_TXn

Vos

VOD

MPC8378E SGMII

SerDes Interface

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