STPMC1 datasheet(65/77 Pages) STMICROELECTRONICS

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STPMC1

Theory of operation

Doc ID 15728 Rev 6

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t3: data value is placed in SDA

t4: SDA value is stable and shifted into the device

t3 −> t5 (> 10 µs): writing clock period

t3 −> t5: 1 bit data value

t5 −> t6: 6 bits address of the destination latch

t6 −> t7: 1 bit EXE command

t8: end of SPI writing

t9: SPI enters idle state

9.21.4

Interfacing the standard 3-wire SPI with STPMC1 SPI

Due to the fact that a 2-wire SPI is implemented in the STPMC1, it is clear that sending any

command from a standard 3-wire SPI would require 3-wire to 2-wire interface, which should

produce a proper signal on SDATD from host signals SDI, SDO and SYN. A single gate 3-

state buffer could be omitted by an emulation of SPI just to send some command. On a

microcontroller this would be done by the following steps:

disable the SPI module

set SDI pin which is connected to SDATD to be output

activate SYN first and then SCS

apply new bit value to SDI and activate SCL

deactivate SCL

repeat the last two steps seven times to complete one byte transfer

repeat the last three steps for any remaining byte transfer

set SDI pin to be input

deactivate SCS and the SYN

10. enable the SPI module

In case of precharge command (0xFF), emulation above is not necessary. Due to the pull up

device on the SDATD pin of the STPMC1 the processor needs to perform the following

steps:

activate SYN first in order to latch the result;

after at least 1 s activate SCS

write one byte to the transmitter of SPI (this produces 8 pulses on SCL with SDI = 1)

deactivate SYN

optionally read the data records (the sequence of reading is altered

deactivate SCS

9.21.5

Permanent writing of the CFG bits

In order to make a permanent set of some CFG bits, the following procedure should

be conducted:

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