STA321 datasheet(66/157 Pages) STMICROELECTRONICS

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Serial audio interface

STA321

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Doc ID 15351 Rev 3

Serial audio interface

The data on pins SDATAI, SDATAO, LRCLKI and LRCLKO are always synchronous with the

bit clock. The data on these pins changes with the BICLK active (or clocking) edge.

The BICLK strobe edge latches the data SDATAI, SDATAO, LRCLKI, LRCLKO; thus this

data should be stable near the BICLK strobe edges. The slave device uses the strobe edges

to latch the serial data internally.

The active and strobe edges can be selected to be the rising edge or the falling edge by

appropriately programming register bits SAI_IN1_CFG0[7], SAI_OUT_CFG0[7] and

SAI_IN2_CFG0[7].

The serial-to-parallel interface and the parallel-to-serial interface can have different

sampling rates. Figure 41 shows a typical setup.

Figure 41.

SAI typical sampling rates

11.1

Master mode

In this mode BICLKI/BICLKO and LRCLKI/LRCLKO are configured as outputs and are

generated by the core.

Figure 42.

Timing diagram for master mode

SAI_out

PLL

CLK

98 MHz

SAI_in

Sample rate

converter

Fs = 8 - 192 kHz

Fs = CLK / 1024

96 kHz

Processing

Fs = CLK / 1024

96 kHz

Fs = CLK / 2048

96 kHz or

48 kHz

Fs = CLK / 1024

Biclki/

Biclko

BICLKI

BICLKO

LRCLKI

LRCLKO

SDATAO

SDATAI

tDL

tDDA

tDST

tDHT

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