STA321 datasheet(32/157 Pages) STMICROELECTRONICS

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Clock management

STA321

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Doc ID 15351 Rev 3

Voltage controlled oscillator (VCO)

This is the oscillator inside the PLL, which produces a frequency, fVCO, on output FVCO

proportional to the input control voltage.

Input frequency divider (IDF)

This frequency divider divides the PLL input clock CLKIN by the input division factor (IDF) to

generate the PFD input frequency. IDF is programmed in register PLLCFG0[3:0].

Loop frequency divider (LDF)

This frequency divider is present within the PLL for dividing the VCO output by the loop

division factor (LDF). LDF is programmed in register bits PLLCFG3[5:0].

Lock circuit

The output of this block, signal LOCKP, is asserted high when the PLL enters the state of

coarse lock in which the output frequency is ±10% of the desired frequency. LOCKP is

refreshed every 32 cycles of F_INT. The status bit PLL_UNLOCK is in register PLLST on

page 132.

5.3.2

Output frequency computation

The input clock frequency of the phase/frequency detector (PFD) is

fF_INT = CLKIN / IDF

The VCO frequency depends on the value of register bit PLLCFG0.PLL_FR_CTRL such

that

When PLL_FR_CTRL = 1

fVCO = fF_INT * (LDF + FRAC / 2

16 + 1 / 217)

and when PLL_FR_CTRL = 0

fVCO = fF_INT * LDF

Notes:

1. When dither is disabled (PLL_DDIS = 1), the factor 1 / 217 is not used in the multiplication.

2. There are some limits to the input and output frequencies as given in Table 17 and

Table 18 when selecting the values for IDF, LDF, and FRAC.

3. The LDF values of 5, 6 and 7 cannot be used when fractional synthesis mode is on, that

is, when PLL_FR_CTRL = 1.

4. The fractional control bits (FRAC_INPUT) must be set to the required values before

activating the fractional synthesis mode.

Table 17.

Input division factor (IDF)

IDF[3]

IDF[2]

IDF[1]

IDF[0]

Input division factor (IDF)

000

001

010

…

………

…

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