STA321 datasheet(35/157 Pages) STMICROELECTRONICS

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STA321

Digital processing stage

Doc ID 15351 Rev 3

35/157

Figure 15.

SAI_out data multiplexer

6.2

Sampling rate converter

The sample rate converter (SRC) re samples the input data source in order to send to the

processing block an audio stream always with a fixed frequency:

sampling frequency, fS = fsys_clk / 1024 where fsys_clk is the system clock frequency.

In all the examples given here, fS = 96 kHz.

Figure 16.

Sample rate converter block diagram

The selection between x2 FIR interpolation and direct input data is made automatically by

the threshold selector block. If the input sampling frequency (measured by the DRLL) is

higher than the SRC threshold (that is, more than 81 kHz) the direct connection is selected

(first filter bypassed), otherwise the first x2 filter is added to the data path.

A 3-kHz hysteresis is fixed around the SRC threshold nominal value in order to prevent

unstable oscillations.

ADC (L/R)

000

SAI_out1

SAI_in1 (L/R)

001

SAI_in2 (L/R)

010

SRC1 (L/R)

011

SRC2 (L/R)

100

PROC (ch0/ch1)

101

PROC (ch2/ch3)

else

P2SDATA[5:3]

ADC (L/R)

000

SAI_out2

2-channel signal

1-channel signal

SAI_in1 (L/R)

001

SAI_in2 (L/R)

010

SRC1 (L/R)

011

SRC2 (L/R)

100

PROC (ch0/ch1)

101

PROC (ch2/ch3)

else

P2SDATA[2:0]

Interpolation

FIR x2

Threshold

selector

DRLL

Interpolation

FIR x2

Precomp.

FIR

Sync 6

async.

Data input

LRCK_IN

Ratio

Data output

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