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STA321 Scheda tecnica(PDF) 132 Page - STMicroelectronics |
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STA321 Scheda tecnica(HTML) 132 Page - STMicroelectronics |
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132 / 157 page ![]() Register description STA321 132/157 Doc ID 15351 Rev 3 PLLPFE Address: 0xC4 Type: RW Reset: 0x80 Description: PLLST PLL status Address: 0xC5 Type: RO Reset: 0x00 Description: 76 54 32 10 PLL_BYP_UNL BICLK2PLL PLL_PWDN PLL_NOPDDIV Reserved [7] PLL_BYP_UNL 0: PLL clock is not bypassed if it is unlock 1: PLL clock is bypassed if it is unlock, the external clock is used as system clock [6] BICLK2PLL PLL clock in selection 0: normal behaviour 1: BICLKI1 is used as PLL clock source [5] PLL_PWDN 0: normal behaviour 1: PLL goes into power-down mode [4] PLL_NOPDDIV 0: PLL goes to power-down when the divider settings are changed 1: PLL remains active when the divider settings are changed [3:0] Reserved 76 54 32 10 PLL_UNLOCK PLL_PWD_ST PLL_BYP_ST Reserved [7] PLL_UNLOCK 0: normal behaviour 1: PLL is not locked [6] PLL_PWD_ST 0: normal behaviour 1: PLL is in power-down mode [5] PLL_BYP_ST 0: PLL is selected 1: PLL is bypassed |
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