WM9093ECSSLASHR datasheet(35/84 Pages) WOLFSON

35 / 84 page

Production Data

WM9093

PD, March 2012, Rev 4.2

Figure 5 Zobel Network Components for HPL and HPR

CLOCKING CONTROL

The internal clocks for the WM9093 are derived from a common internal clock source, CLK_SYS.

This clock is the reference for the Control Write Sequencer, Class D switching amplifier, DC servo

control and other internal functions.

CLK_SYS is derived from an internal oscillator; this is controlled by the OSC_ENA register. The

frequency of CLK_SYS is nominally 6MHz; internal dividers generate the other required clocks from

this reference.

A slow clock, TOCLK, is used to set the timeout period for volume updates when zero-cross detect is

used. This clock is derived from CLK_SYS and is enabled by TOCLK_ENA. The slow clock frequency

selected

using

the

programmable

dividers

TOCLK_RATE,

TOCLK_RATE_X4

and

TOCLK_RATE_DIV16. See Table 17 for a list of possible TOCLK rates.

The clocking configuration is illustrated in Figure 6. The control registers associated with WM9093

Clocking are defined in Table 16.

OSC_ENA

CLK_SYS

f/N

DC Servo clock

f/N

Class D switching clock

f/N

256kHz clock to

Charge Pump, Control

Write Sequencer and

other circuits

f.N

TOCLK_ENA

Volume update timeout

f/N

f/1024

TOCLK_RATE_X4

0 = f x 1

1 = f x 4

TOCLK_RATE

0 = f / 2

1 = f / 1

Internal

Oscillator

f/N

TOCLK_RATE_DIV16

0 = f / 1

1 = f / 16

Figure 6 Clocking Scheme

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