WM9093ECSSLASHR datasheet(45/84 Pages) WOLFSON

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Production Data

WM9093

PD, March 2012, Rev 4.2

Generic Shut-Down

The Generic Shut-Down sequence can be initiated by writing 0110h to Register 73 (49h). This single

operation starts the Control Write Sequencer at Index Address 16 (10h) and executes the sequence

defined in Table 22.

This sequence takes approximately 2.8ms to run.

WSEQ

INDEX

ADDRESS

WIDTH

START

DATA

DELAY

EOS

DESCRIPTION

16 (10h)

R96 (60h)

7 bits

Bit 1

00h

HPOUT1R_DLY = 0

HPOUT1R_OUTP = 0

HPOUT1R_RMV_SHORT = 0

HPOUT1L_DLY = 0

HPOUT1L_OUTP = 0

HPOUT1L_RMV_SHORT = 0

(delay = 0.5ms)

17 (11h)

R84 (54h)

2 bits

Bit 0

00h

DCS_ENA_CHAN_0 = 0

DCS_ENA_CHAN_1 = 0

(delay = 0.5ms)

18 (12h)

R1 (01h)

2 bits

Bit 8

00h

HPOUT1R_ENA = 0

HPOUT1L_ENA = 0

(delay = 0.5ms)

19 (13h)

R76 (4Ch)

1 bit

Bit 15

00h

CP_ENA = 0

(delay = 0.5ms)

20 (14h)

R1 (01h)

2 bits

Bit 12

00h

SPKOUTL_ENA = 0

(delay = 0.5ms)

Table 22 Generic Shut-Down Default Sequence

POWER SEQUENCES AND POP SUPPRESSION CONTROL

The WM9093 incorporates a number of features, including Wolfson’s SilentSwitch™ technology,

designed to suppress pops normally associated with Start-Up, Shut-Down or signal path control. To

achieve maximum benefit from these features, careful attention is required to the sequence and

timing of these controls. Note that, under the recommended usage conditions of the WM9093, these

features will be configured by running the default Start-Up and Shut-Down sequences as described in

the “Control Write Sequencer” section. In these cases, the user does not need to set these register

fields directly. Additional bias controls, also pre-programmed into Control Write Sequencer, are

described in the “Reference Voltages and Master Bias” section.

INPUT VMID CLAMPS

The analogue inputs are biased to VMID in normal operation. In order to avoid audible pops caused

by enabling the inputs, the WM9093 can clamp the input pins to VMID when the relevant input stage

is disabled. This allows pre-charging of the input AC coupling capacitors during power-up.

The Input VMID Clamps connect the input pins to a buffered VMID reference. The buffered VMID

reference is enabled by setting VMID_BUF_ENA. The VMID Clamp is enabled on each pair of input

pins independently using the register bits defined in Table 23.

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