WM9093ECSSLASHR datasheet(37/84 Pages) WOLFSON

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Production Data

WM9093

PD, March 2012, Rev 4.2

CONTROL INTERFACE

The WM9093 is controlled by writing to registers through a 2-wire serial control interface. Readback is

available for all registers, including Chip ID and power management status.

The WM9093 is a slave device on the control interface; SCL is a clock input, while SDA is a bi-

directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same

interface, the WM9093 transmits logic 1 by tri-stating the SDA pin, rather than pulling it high. An

external pull-up resistor is required to pull the SDA line high so that the logic 1 can be recognised by

the master. Note that the control interface can support I/O levels up to 2.7V.

In order to allow many devices to share a single 2-wire control bus, every device on the bus has a

unique 7-bit device ID (this is not the same as the 8-bit address of each register in the WM9093). The

WM9093 device ID is 1101_1100 (DCh). The LSB of the device ID is the Read/Write bit; this bit is set

to logic 1 for “Read” and logic 0 for “Write”.

The WM9093 operates as a slave device only. The controller indicates the start of data transfer with a

high to low transition on SDA while SCL remains high. This indicates that a device ID, register

address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in

the next eight bits on SDA (7-bit device ID + Read/Write bit, MSB first). If the device ID received

matches the device ID of the WM9093, then the WM9093 responds by pulling SDA low on the next

clock pulse (ACK). If the device ID is not recognised or the R/W bit is ‘1’ when operating in write only

mode, the WM9093 returns to the idle condition and waits for a new start condition and valid address.

If the device ID matches the device ID of the WM9093, the data transfer continues as described

below. The controller indicates the end of data transfer with a low to high transition on SDA while SCL

remains high. After receiving a complete address and data sequence the WM9093 returns to the idle

state and waits for another start condition. If a start or stop condition is detected out of sequence at

any point during data transfer (i.e. SDA changes while SCL is high), the device returns to the idle

condition.

The WM9093 supports the following read and write operations:



Single write



Single read



Multiple write using auto-increment



Multiple read using auto-increment

WM9093ECS/R Scheda tecnica(PDF) 37 Page - Wolfson Microelectronics plc