TLC32046MFKB datasheet(16/56 Pages) TI

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2–2

2.1

Internal Timing Configuration (see Figure 2–1)

All the internal timing of the AIC is derived from the high-frequency clock signal that drives the master clock

input. The shift clock signal, which strobes the serial port data between the AIC and DSP, is derived by

dividing the master clock input signal frequency by four.

The TX(A) counter and the TX(B) counter, which are driven by the master clock signal, determine the D/A

conversion timing. Similarly, the RX(A) counter and the RX(B) counter determine the A/D conversion timing.

In order for the low-pass switched-capacitor filter in the D/A path (see Functional Block Diagram) to meet

its transfer function specifications, the frequency of its clock input must be 288 kHz. If the clock frequency

is not 288 kHz, the filter transfer function frequencies are frequency-scaled by the ratios of the clock

frequency to 288 kHz:

Absolute Frequency (kHz)

Normalized Frequency

SCF f

clock

(kHz)

288

For Low-Pass SCF f

clock u

288 kHz, please call the factory.

(1)

To obtain the specified filter response, the combination of master clock frequency and the TX(A) counter

and the RX(A) counter values must yield a 288-kHz switched-capacitor clock signal. This 288-kHz clock

signal can then be divided by the TX(B) counter to establish the D/A conversion timing.

The transfer function of the band-pass switched-capacitor filter in the A/D path (see Functional Block

Diagram) is a composite of its high-pass and low-pass transfer functions. When the shift-clock frequency

(SCF) is 288 kHz, the high-frequency roll-off of the low-pass section will meet the band-pass filter transfer

function specification. Otherwise, the high-frequency roll-off is frequency-scaled by the ratio of the

high-pass section SCF clock to 288 kHz (see Figure 5–5). The low-frequency roll-off of the high-pass section

meets the band-pass filter transfer function specification when the A/D conversion rate is 16 kHz. If not, the

low-frequency roll-off of the high-pass section is frequency-scaled by the ratio of the A/D conversion rate

to 16 kHz.

The TX(A) counter and the TX(B) counter are reloaded each D/A conversion period, while the RX(A) counter

and the RX(B) counter are reloaded every A/D conversion period. The TX(B) counter and the RX(B) counter

are loaded with the values in the TB and RB registers, respectively. Via software control, the TX(A) counter

can be loaded with the TA register, the TA register less the TA

′ register, or the TA register plus the TA′ register.

By selecting the TA register less the TA

′ register option, the upcoming conversion timing occurs earlier by

an amount of time that equals TA

′ times the signal period of the master clock. If the TA register plus the TA′

option is executed, the upcoming conversion timing occurs later by an amount of time that equals

′ times the signal period of the master clock. Thus, the D/A conversion timing can be advanced or

retarded. An identical ability to alter the A/D conversion timing is provided. However, the RX(A) counter can

be programmed via software control with the RA register, the RA register less the RA

′ register, or the RA

′ register.

The ability to advance or retard conversion timing is particularly useful for modem applications. This feature

allows controlled changes in the A/D and D/A conversion timing and can be used to enhance signal-to-noise

performance, to perform frequency-tracking functions, and to generate nonstandard modem frequencies.

If the transmit and receive sections are configured to be synchronous, then the low-pass and band-pass

switched-capacitor filter clocks are derived from the TX(A) counter. Also, both the D/A and A/D conversion

timings are derived from the TX(A) counter and the TX(B) counter. When the transmit and receive sections

are configured to be synchronous, the RX(A) counter, RX(B) counter, RA register, RA

′ register, and RB

registers are not used.

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