TLC32046MFKB datasheet(21/56 Pages) TI

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2–7

Low-pass A D SCF clock frequency

master clock frequency

R(A)

High-pass SCF clock frequency (A D channel)

+ A D conversion frequency

(2)

Conversion frequency:

D A conversion frequency

low-pass D A SCF clock frequency

T(B)

A D conversion frequency

low-pass A D SCF clock frequency (for low pass receive filter)

R(B)

(3)

NOTE: T(A), T(B), R(A), and R(B) are the contents of the TA, TB, RA, and RB registers, respectively.

2.11 Operation of TLC32046 With Internal Voltage Reference

The internal reference of the TLC32046 eliminates the need for an external voltage reference and provides

overall circuit cost reduction. The internal reference eases the design task and provides complete control

of the IC performance. The internal reference is brought out to REF. To keep the amount of noise on the

reference signal to a minimum, an external capacitor can be connected between REF and ANLG GND.

2.12 Operation of TLC32046 With External Voltage Reference

REF can be driven from an external reference circuit. This external circuit must be capable of supplying

250

µA and must be protected adequately from noise and crosstalk from the analog input.

2.13 Reset

A reset function is provided to initiate serial communications between the AIC and DSP and to allow fast,

cost-effective testing during manufacturing. The reset function initializes all AIC registers, including the

control register. After a negative-going pulse on RESET, the AIC is initialized. This initialization allows

normal serial port communications activity to occur between AIC and DSP (see AIC DX Data Word Format

section). After RESET, TA=TB=RA=RB=18 (or 12 hexadecimal), TA

′=RA′=01 (hexadecimal), the A/D

high-pass filter is inserted, the loop-back function is deleted, AUX IN+ and AUX IN – are disabled, transmit

and receive sections are in synchronous operation, programmable gain is set to 1, the on-board (sin x)/x

correction filter is not selected, D10OUT is set to 0, and D11OUT is set to 0.

2.14 Loopback

This feature allows the circuit to be tested remotely. In loopback, OUT+ and OUT– are internally connected

to IN+ and IN –. The DAC bits (D15 to D2), which are transmitted to DX, can be compared with the ADC bits

(D15 to D2), received from DR. The bits on DR equal the bits on DX. However, there is some difference in

these bits due to the ADC and DAC output offsets.

The loopback feature is implemented with digital signal processor control by transmitting a logic 1 for data

bit D3 in the DX secondary communication to the control register (see Table 2–3).

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