CS22210 datasheet(11/31 Pages) CIRRUS

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CS22210 PCI/USB Wireless Controller

11 of 31

D556PP2

Rev. 3.0

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SMA6

Output

Address bit6. Also shared as boot-rom address bit6. Also used during

reset to latch in the strap value for freq_sel(0). Freq_sel(2:0) is used to

select the multiplication factor for the internal PLL (000=1x, and 111=8x).

SMA7

Output

Address bit7. Also shared as boot-rom address bit7. Also used during

reset to latch in the strap value for freq_sel(1). Freq_sel(2:0) is used to

select the multiplication factor for the internal PLL (000=1x, and 111=8x).

SMA8

Output

Address bit8. Also shared as boot-rom address bit8. Also used during

reset to latch in the strap value for freq_sel(2). Freq_sel(2:0) is used to

select the multiplication factor for the internal PLL (000=1x, and 111=8x).

SMA9

Output

Address bit9. Also shared as boot-rom address bit9. Also used during

reset to latch in the strap value for sdram_delay(0). Sdram_delay(2:0) is

used to select the delay factor for the internal memory clock (000=0ns,

and 111=1.75ns with each .25ns increments).

SMA10

Output

Address bit10. Also shared as boot-rom address bit10. Also used during

reset to latch in the strap value for sdram_delay(1). Sdram_delay(2:0) is

used to select the delay factor for the internal memory clock (000=0ns,

and 111=1.75ns with each .25ns increments).

SMA11

Output

Address bit11. Also shared as boot-rom address bit11. Also used during

reset to latch in the strap value for sdram_delay(2). Sdram_delay(2:0) is

used to select the delay factor for the internal memory clock (000=0ns,

and 111=1.75ns with each .25ns increments).

SMD[7:0]

Bi-directional

Data bus. The data bus contains the data to be written to memory on a

writecycle andthe read return dataonareadcycle.

SMD[15:8]

Bi-directional

Shared data bus. The data bus contains the data to be written to RAM

memory on a write cycleand thereadreturndataona read cycle. Data bit

[15:8] is also shared as boot ROM address bit [19:12].

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