CS22210 datasheet(16/31 Pages) CIRRUS

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CS22210 PCI/USB Wireless Controller

16 of 31

D556PP2

Rev. 3.0

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nCBE[3:0]

Bi-directional

Control/byte enable. This bus defines the bus command during the first

clock of a PCI transaction and the data byte enables during subsequent

clocks.

IDSEL

I/O OD

PCI initialization device select. Used as a chip select during configuration

read and write cycles.

nFRAME

Bi-directional

PCI cycle frame.

This signal marks the beginning and duration of a

current bus cycle.

NIRDY

Bi-directional

PCI initiator ready. IRDY holds off the beginning of a write cycle and the

completion of a read cycle until sampled active.

nTRDY

Bi-directional

PCI target ready. This signal is driven active to indicate that write data

has been sampled or that read data has been delivered.

nDEVSEL

Bi-directional

PCI device select. As a medium speed device, this signal is driven active

two PCI clocks after NFRAME is sampled active, indicating a positive

decode. It remains active until the end of the transaction.

nSTOP

Bi-directional

PCI stop. This signal indicates a target initiated termination of the current

cycle.

nINTA

Output/Open Drain

PCI interrupt request A. Generates an interrupt on the PCI bus.

PCLK

I/O OD

PCI clock. Typically a 33 MHz. All CS22210 PCI activity is synchronous to

PCLK.

nPERR

Bi-directional

PCI parity error. This signal is asserted two clocks after a data parity error

is detected on the PCI bus.

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