RM0319 datasheet(58/368 Pages) STMICROELECTRONICS

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Multiport DDR controller (MPMC)

RM0319

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Doc ID 022640 Rev 3

Configured options

Each AHB port in the memory controller has been defined for the requirements of the

intended system. The configured options are:

Type of interface

All ports of the MPMC are clock domain programmable relative to the main core clock.

These ports initialize in asynchronous operation, but can be changed by programming the

associated ahbY_fifo_type_reg parameter. For more information on setting this parameter,

refer to Port clocking.

Asynchronous FIFOs handle the clock domain crossing when operating in any of the non

synchronous modes. Refer to Table 15: Configured AHB settings, for the clock relativity for

each port.

Note:

When switching between asynchronous and synchronous mode of operation, ensure that

there are no outstanding transactions on the port whose behaviour is being changed. If

transactions are waiting, there may be unexpected loss of data or a lockout condition on that

AHB port.

Datapath width

Each port has a data interface width of 32 bits.

READ and WRITE command Lengths for INCR Operations

AHB ports handle sequential requests of unspecified length (INCR) by issuing block data

requests of the size programmed in the associated ahbX_wrcnt or ahbX_rdcnt parameter

(where X is the port number). If the request is larger than the value programmed in that

parameter, the request will be divided into multiple requests. Subsequent read commands

will be issued when the last word of data has been delivered back to the requesting AHB

port. Subsequent WRITE commands will be issued after the last data word of the previous

request has been transferred from the AHB interface to the memory controller core. The

value defined in each parameter should be a multiple of the number of bytes in the AHB bus

width. For this memory controller, since the AHB bus width is 32 bits, these parameters

should be programmed to 4, 8, 12, 16, etc. up to 1024 bytes.

Port FIFO depths

Each data port contains a read, a write and a command FIFO. The depth of each buffer in

each port is listed in Table 15: Configured AHB settings.

Error detection

When an illegal operational condition is detected on a new AHB transaction entering the

port, the port responds with an ERROR.

Port clocking

There are four user-selectable modes of operation for each of the AHB memory controller

port interfaces.

The mode is set by programming the corresponding ahbY_fifo_type_reg parameter. The

four settings are:

●

Synchronous ('b11)

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