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RM0319 Scheda tecnica(PDF) 61 Page - STMicroelectronics

Il numero della parte RM0319
Spiegazioni elettronici  SPEAr320S architecture and functionality
PDF  368 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

RM0319 Scheda tecnica(HTML) 61 Page - STMicroelectronics

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RM0319
Multiport DDR controller (MPMC)
Doc ID 022640 Rev 3
61/368
WRAPx transactions with a starting address that is not aligned to the total number of bytes
in the burst (bytes-per-beat times the number of beats) are issued as two separate memory
controller core transactions as shown in Figure 17. The first transaction has a starting
address which is the same as the WRAP transaction starting address and its byte count is
the number of bytes from the starting address to the wrap boundary. The second transaction
has a starting address which is aligned to the byte count in the WRAPx transfer and its byte
count is the number of bytes from the wrapped address back to the starting address. This
means that an AHB WRAP instruction is divided into two core transactions, one for the non-
wrapped portion of the transaction and one for the wrapped portion. The starting address
determines whether the WRAP transaction will actually wrap or not. A wrap transaction with
an aligned address is equivalent to an INCRx command and is treated as such by the AHB
port.
Figure 17.
WRAPx effective transaction
Full-Size INCR transactions
Since the MPMC core bus protocol does not support transactions of an unspecified length,
AHB INCR transactions require special handling by the AHB port logic. Each AHB port
contains a pair of programmable parameters for determining the length of a command that
will be issued to the MPMC core when an INCR command is issued to the AHB port. These
parameters are ahbX_wrcnt and ahbX_rdcnt and they hold the programmed size used for
an unspecified length WRITE and a READ command length in bytes for port X when this
type of command is issued to the core.
The value defined in these parameters should be a multiple of the number of bytes in a data
word for the core. If that is not the case, the parameter values will automatically be truncated
to the data word boundary. Clearing these parameters will cause the port to issue
commands of 0 length to the core, which the core interprets as the pre-configured value of
1024.
The values for the ahbX_wrcnt and ahbX_rdcnt parameters should be chosen carefully and
should be based on the average length of an INCR transaction expected from the AHB
master. If the values are programmed too low, the AHB port must issue a large number of
small core transactions that may fill up the command queue and reduce system
performance. A full queue may also inhibit higher priority requests from meeting their
latency requirements. On the other hand, if the values for the parameters are programmed
Starting
Address
Wrap
Address
The command wraps at address:
(Starting Address+X)-Modules(Starting Address/X)
Where X is the Wrap Size in WARPx
Starting Address-Modules (Starting Address/X)
Where X is the Wrap Size in WARPx
WRAPx Command
Length = X*ahbX_HSIZE
Transaction #1
Transaction #2
Memory Page Containing Starting Address



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